1. Field of the Invention
The present invention relates to a magnetic disk apparatus, more particularly to a write data fetching circuit, provided in a magnetic disk apparatus, which fetches write data for an encoding circuit of one of the run-length-limited (RLL) codes, i.e., a (1-7) RLL code.
2. Description of the Related Art
To increase the capacity of magnetic disk apparatuses, the following methods are used: a. increasing the number of magnetic disks, b. raising the track density of the magnetic disks, c. raising the bit density, etc. The method a. can be easily realized, but since the number of disks increases, the cost of the product also rises. The method b. cannot be easily realized, so considerable development costs and time are required. The method c. is advantageous in terms of both product cost and development costs, so it is most often used for achieving larger capacities of magnetic disk apparatuses.
To raise the bit density of the magnetic disks, it is necessary to select a suitable recording code. That is, when the SN ratio, head floating height, thickness of the recording medium, magnetic characteristics, and other conditions are set, the recording code is selected so as to maximize the planar density. In this case, consideration is given to the characteristics of the magnetic recording medium, and it is demanded that the code be resistant to defects of the magnetic medium and intersymbol interference and that a high recording density can be obtained.
To satisfy these demands, use is currently made of the non-return zero inversion (NRZI), 4/5 GCR, modified frequency modulation (MFM), run-length-limited (RLL), and other coding methods. The Rll code requires the presence of a minimum (d) and maximum (k) slots in the transition between two codes and is thus called a "(d-k) RLL code". For example, the RLL code includes a (2-7) RLL code and (1-7) RLL code. The (2-7) RLL encoding method is disclosed in, for example, the specification of U.S. Pat. No. 3,689,899, and the (1-7) RLL encoding method is disclosed in the specification of U.S. Pat. No. 4,488,142.
The frequency of the clock used in the transmission and reception of data between a magnetic disk apparatus using a (2-7) RLL code and the control apparatus of the host controller is a fundamental frequency (1f), but in the (2-7) RLL-code encoding circuit in the magnetic disk apparatus, the frequency of the clock is two times the fundamental frequency (2f). This double frequency 2f clock is prepared by a servocircuit in the magnetic disk apparatus. Below, this double frequency 2f clock will be abbreviated as VFO2F.
Since the fundamental frequency 1f and the VFO2F prepared in the magnetic disk apparatus are asynchronous, when fetching data from the control circuit to the encoding circuit in the magnetic disk apparatus, it is necessary to synchronize the fundamental frequency 1f with the clock VFO1F, which consists of the VFO2F prepared by the magnetic disk apparatus divided in half and which has the same frequency as the fundamental frequency. In this case, it is necessary to synchronize with the clock VFO1F of the fundamental frequency no matter what the state, so the VFO1F is made a two-phase clock so that data can be fetched. The VFO1F and two-phase clock signal at this time can be easily prepared from the VFO2F in the magnetic disk apparatus.
Even in a magnetic disk apparatus using the (1-7) RLL signal, the fundamental frequency for transmission and reception of data between the control circuit and encoding circuit is 1f just as in the case of use of a (2-7) RLL code.
However, a (1-7) RLL-code encoding circuit operates on a clock (3/2 )f of a frequency 1.5 times the fundamental frequency 1f. In this case, the magnetic disk apparatus issues a clock VFO3F having a frequency 3f three times the fundamental frequency. By dividing this, a clock VFO3/2F is prepared having a frequency 3/2 times the fundamental frequency.
The transmission and reception of data performed between the control circuit and encoding circuit are performed by a clock of the fundamental frequency 1f, so it is necessary to divide the VFO3F prepared in the magnetic disk apparatus by three to prepare a clock VFO1F having a fundamental frequency and to synchronize it with the fundamental frequency 1f.
In the case of the (1-7) RLL signal, as explained in detail next, it is necessary to prepare a precise clock VFO1F with a duty ratio of 50 percent and to synchronize it with the fundamental frequency 1f. However, a clock of a digital signal with a high frequency differs from an analog signal. It is extremely difficult to precisely divide it into 1/m, where m is any number other than 2.sup.n, except 1/2.sup.n, where n is an integer. Therefore, the resultant frequency-division circuit cannot have sufficient precision and stability.
The above problems will be explained later with reference to the drawings.